To save power in datacenters and other data-intensive applications, a typical 12V DC distribution bus can be replaced by a higher voltage bus e.g. typically 48V nominal. This higher distribution voltage is stepped down on the motherboard in one or more stages to the low DC voltage required by the CPU (central processing unit), memory, and other electronic components included in the system such as memory, graphics logic, I/O (input/output), etc. For example, a single DC/DC converter conventionally generates an intermediate bus voltage that is fed to all lower-voltage converter stages. The intermediate bus is typically between 5-12V and can therefore use existing infrastructure to be highly scalable. In another example, the CPU has a dedicated converter (e.g. 48V to 1V) that can be a single conversion stage, or two converter stages in series to achieve the step down. The other voltage rails (e.g. memory, graphics logic, etc.) are fed from a common intermediate bus. In still another example, all voltage rails are fed directly from the 48V distribution bus. In this case scalability is limited, and the use of existing infrastructure is not an option. Other architectures employ multiple intermediate bus voltages for feeding different voltage rails, using direct conversion for the CPU and some other voltage rails with the intermediate bus powering the rest, or some combination thereof.
In each case, the final conversion stage of the DC/DC converter that supplies the CPU is widely known as a voltage regulator. The voltage regulator converts an intermediate voltage e.g. 12V to the CPU voltage e.g. 1V. The CPU communicates with the voltage regulator using a protocol for status, protection, and system optimization. Part of the optimization includes instructing the voltage regulator to enter power saving modes of operation to increase light-load efficiency when the CPU enters low power states. However, a problem occurs with higher-voltage distribution systems such as 48V systems when the converter stage that converts the high distribution bus voltage to an intermediate bus voltage is not privy to the communication between the CPU and the voltage regulator that converts between the intermediate bus voltage and the load voltage. For example in a 48V system, the 48V-to-12V converter stage monitors its output current and adjusts its operating point (e.g. active phases, pulse frequency modulation (PFM) mode, etc.) accordingly. However, if the voltage regulator is still in the most active power state but the 48V-to-12V converter stage enters a low power mode, the slow response of the 48V-to-12V converter stage can feed through to the CPU voltage rail when a transient occurs. Such a condition would result in a CPU hang which is prohibited in a server where high reliability is a fundamental necessity.
This problem has been solved by increasing the intelligence of the converter stage that converts the high distribution bus voltage to an intermediate bus voltage. For example, this intermediate converter stage can measure its output voltage and current, and make decisions to enter power-saving states based on those measurements. Detection of a transient event may cause the intermediate converter stage to leave the power saving state by adding phases (if applicable) or leaving pulse frequency modulation (PFM) mode and entering PWM (pulse width modulation) mode. However, to maintain high efficiency, converters on a higher-voltage distribution bus such as a 48V bus typically switch at lower frequencies than the downstream lower voltage regulators that feed the CPUs. Further, the filter inductance of these higher-voltage converter stages is significantly larger than that of the downstream voltage regulators, by more than an order of magnitude. As such, their response is significantly slower.
During low current intervals in the maximum power state, it is possible that a voltage regulator sheds phases to conserve power. The multiple phases, high switching frequency, and low inductance promote fast reaction time to allow the voltage regulator to respond quickly to a load transient without the CPU voltage experiencing undershoot. However, the response of the upstream higher-voltage converter stage is significantly slower than the voltage regulator. Therefore, if the converter stage that converts the high distribution bus voltage to the intermediate bus voltage enters a power saving state while the CPU is still in the maximum power state, the slow response of this intermediate converter stage generates a sag on the intermediate voltage input to the voltage regulator which in turn propagates and manifests itself as undershoot at the CPU.